The FMC board receives the analogue, provides impedance matching (termination), passes it through the line receiver and drives the ADC through the low pass filter.

There are 16 ADC channels implemented as 8 dual-channel (simultaneous sampling) 8 or 10 bit pipelined ADCs running at 100 or 125MHz. The outputs of the ADCs are connected to the FPGA equipped with 1Gbit DDR-3 SDRAM. The Xilinx Spartan 6 FPGA is used.

The ADCs are driven by the low jitter clock generator which also generates FPGA clock. The sampling frequency is programmed from 50 to 130MHz. TheThe FMC is equipped with MD5 connector

The on-board FPGA is dedicated to detection of signal and estimation of pulse energy.

The SDRAM memory is used for fast data acquisition in real time.

Features FMC low-pin count 16 simultaneously sampling ADCs 16 differential inputs with amplifiers and low-pass filters samplig freqquency up to 130MHz resolution up to 10bits clock distribution circuit embedded FPGA – Spartan 6, 16k LE embedded 1Gbit of DDR-3 SDRAM 4channel DAC 0-10V