FMC Delay

This delay module will take in a TTL trigger signal and will send it out to four different outputs. The delay from the trigger input to each of the outputs can be set independently in a range from 500 ns to 120 seconds. It is implemented using a dedicated time-to-digital converter IC from the European company Acam.

The project is developed in cooperation with CERN as a part of the Open Hardware Repository initiative (www.ohwr.org)

Features

1 ns resolution or better.
Accuracy: +/- (500 ps + timebase accuracy).
Timebase accuracy: +/- 4ppm.
- Implementation details: timebase from a local TCXO on FMC card and needs calibration. The 4ppm accuracy is the one of the on-board TCXO. Much better accuracy will be reached when used on a White Rabbit enabled FMC carrier.
500 ns - 120 s range or better.
1 input, selectable between front panel and FMC connector. This input is shared by all output channels.
Input electrical standard will be TTL (not LVTTL), with optional 50 Ohm termination. The default power-up state is high impedance. A LED will signal termination status.
External input needs to be protected against +15V pulses with a pulse width of at least 10us @ 50Hz (with protection diodes if possible).
Need to withstand a continuous short-circuit on all the outputs at the same time.
Output standard: 50 Ohm TTL drivers (with 2V/ns or faster rising edges). At power-up the default output state is low, with no glitches.
SMC connectors for input and outputs.
4 individually controllable outputs, with independent delay, width and enable/disable.
Delay circuit reacts on input rising edge. Minimum input pulse width: 100 ns. Pulses shorter than 20ns should be ignored.
Input pulses will be ignored until the longest programmed delay of the previous input pulse has expired.
Output pulse width is programmable in steps of system clock ticks (~125 MHz) with a 16-bit register per output channel.
Jitter will be measured by probing two output channels which have been programmed with the same delay. The sigma of the distribution of delay measurements between the rising edges of any two channels should not exceed 100 ps. This should hold for any programmed delay within the whole delay range.
A circular buffer will contain time tags for at least the last 100 input and output pulses. These time tags will at first be rough UTC (counter initialized by SW) giving ~ms accuracy. Later, with a WR-enabled solution, they can be much more accurate.